Building Blocks for MPEG Stream Processing

In the MPEG-1 multimedia standard, no encoding scheme is defined, but a generally accepted scheme includes the following building blocks: discrete cosine transform, quantization, zig-zag scanning, run-level coding, variable-length encoding, and motion estimation. In this paper, we describe the investigation into how such building blocks can be implemented in reconfigurable hardware, more specifically field-programmable gate arrays (FPGAs). The investigation focuses on the area requirements and the expected speed of such building blocks. Since our investigation will be applied to increase the performance of a programmable processor (running an MPEG-1 software application) augmented with an FPGA structure, we have selected four known to be time-consuming operations for implementation in FPGA: forward discrete cosine transform, the quantization, the Huffman encoding, and the sum of absolute differences. All designs were implemented by writing high-level VHDL code and target two FPGA families from Altera Corp.: FLEX10K and APEX20K. The synthesis results show that the implementations can be clocked between 36 and 162 MHz and that the area utilization is small compared to the largest available FPGA chip within the APEX20K family. Keywords— field-programmable gate array, forward discrete cosine transform, quantization, Huffman encoding, sum of absolute differences